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       Advance in CMOS technology keeps driving the increase of the number of processing cores that can be integrated on a single chip. With the further increase of the number of processing cores, the integration limitations of SoCs become more significant. 3-D integration together with the NoC design paradigm provide a promising solution to overcome these limitations. In this project, we mainly focus on investigating efficient IP mapping and routing schemes for 3-D networks-on-chip.

· Power-Aware Run-Time Incremental Mapping for 3-D NoCs (JCST2013, NPC2011)
      The large number of processing cores integrated into 3-D NoC-based MPSoCs unquestionably offer high parallelism in computation. To better utilize these vast available computation resources, virtualization is applied to allow a single MPSoC to be shared by multiple applications which can be mapped to different networks of the chip at run time. However, the behaviors of the multiple applications vary so dramatically at run time, making it nearly impossible for these applications to be efficiently mapped offline. For these applications, run-time incremental mapping methods should be designed which could not only minimize the overall communication power but also consider future applications whose arrival orders are not known. In addition, in 3-D NoCs, the wire lengths of vertical links (in a few tens of µm) are much shorter than those of horizontal links (in a few thousand µm). As such, more communication could be mapped to vertical links to further reduce transmission delay and power consumption.
      In this work, we propose a novel run-time incremental mapping algorithm which maps applications that can randomly enter and leave an embedded 3-D NoC system while considering the benefits of vertical links. The mapping algorithm tries to minimize overall communication power as well as minimize the impact on future applications (i.e., to reduce the fragmentation caused by small region of tiles). The proposed algorithm is composed of three steps: 1) NoC region selection which selects a cuboid region to reduce the impact on future applications; 2) set matching which allocates the application graph to the sub-regions in different layers such that the vertical links are used as much as possible; and 3) CTG to NoC region mapping which maps the IP cores to the tiles in different sub-regions with minimized total communication power. The higher bandwidth and lower delay properties of the vertical links in 3-D NoC are particularly exploited in set matching and region mapping steps. Experimental results have confirmed that the proposed algorithm saves up to 50% communication power over random mapping and about 20% over a simple heuristic.

·Energy Efficient Multicasting Schemes for 3-D NoC-based SoCs (JSA2013, VLSI-SOC2011)
     It has been observed that following the programming models developed for these 3-D NoC-based SoCs, many applications SoCs exhibit significant one-to-many and one-to-all communications, which mandates efficient multicast support, especially at the hardware level, to help reduce both transmission latency and power consumption. The need of efficient hardware collective communication support is complicated by topological irregularity which might be caused by virtualization or faulty components.
     In this work, two topology oriented multicast routing algorithms, MXYZ and AL+XYZ, are proposed to support multicasting in 3-D NoCs. In specific, MXYZ is a dimension order multicast routing algorithm that targets 3-D NoC systems built upon regular topologies, while AL+XYZ is applicable to NoCs with irregular topologies. If the output channel found by MXYZ is not available (i.e. in the same region), an alternative output channel is used to forward/replicate the packets in AL+XYZ. MXYZ is evaluated against a path based regular topology oriented multicast routing and AL+XYZ against an irregular region oriented multiple unicast routing algorithm. Our experimental results have demonstrated that the proposed MXYZ and AL+XYZ schemes have lower latency and energy consumption than the conventional path based multicast routing and the multiple unicast routing algorithms, meriting them to be more suitable for supporting multicasting in 3-D NoC systems.

· Self-Tuning NoC for Dynamic Network-Flow Dominance Adaptation (NOCS2013)
      Modern networks-on-chip (NoC) systems are required to handle complex run-time traffic patterns and unprecedented applications. Data traffics of these applications are difficult to be fully comprehended at design-time so as to optimize the network design. However, it has been discovered that the majority data flows in a network are dominated by less than 10% of the specific pathways. In this paper, we introduce a method that is capable of identifying critical pathways in a network at run-time and, then, can dynamically reconfigure the network to optimize for the network performance subjected to the identified dominated flows. An online learning and analysis scheme is employed to quickly discover the emerged dominated traffic flows and provides a statistical traffic prediction using regression analysis. The architecture of a self-tuning network is also discussed which can be reconfigured by setting up the identified point-to-point paths for the dominance data flows in large traffic volumes. The merits of this new approach are experimentally demonstrated using comprehensive NoC simulators.