Photonic Networks-on-Chip & Hybrid Opto-Electronic Networks-on-Chip

Photonic Networks-on-Chip (NoC) is considered as a promising candidate to interconnect a large number of processing cores. In this project, our research is mainly focused on investigating energy-efficient photonic and hybrid opto-electronic NoC architectures.

· Generic Wavelength-Routed Optical Router (SOPO2011, IJLT2012)
The heart of a photonic NoC is the on-chip photonic interconnection network which is composed of silicon waveguides and optical routers. In this work, we propose a scalable and non-blocking passive optical router design using micro-ring resonators (MRRs), namely the generic wavelength-routed optical router (GWOR). Fig. 1 shows the 4x4 GWOR which has four bidirectional ports located at four directions, north (N), west (W), south (S), and east (E). Two horizontal and two vertical waveguides are used. Each waveguide is dedicated for direct connection between an input-output pair denoted by I_i->O_3-i (where i =0, 1, 2 or 3). For each waveguide, it has one intersection with each one of the waveguides on the orthogonal direction. For GWOR, non-blocking routing is realized by assigning MRRs to the appropriate corners of the waveguide intersections so that all input light signals can be directed to their destined output ports. As shown Fig. 1, eight MRRs with two resonance wavelengths are used in 4x4 GWOR.

Figure 1 4x4 GWOR.

     Large size GWORs can be constructed using 4x4 GWOR as the basic building block. The wavelength assignment schemes are derived for GWORs with even and odd number of input/output ports. A NxN GWOR needs N-1 input wavelengths, and N(N-2) (for N=2n) or (N-1)² (for N=2n+1) MRRs for routing. Compared with the existing non-blocking router designs, GWOR uses the least number of MRRs and has the least power loss. In addition, the passive nature of GWORs excludes the power needed to drive the tuning and control circuits of those active routers. These advantages make the proposed GWOR a useful building block for future power-efficient photonic NoCs.

· Circuit-Switched On Chip Photonic Interconnection Network (GroupIVCircuit2012)
      In this work, a novel circuit-switched on chip photonic interconnection network (CSPIN) architecture is proposed. Different from existing circuit-switched photonic networks, CSPIN eliminates the electronic control layer but employs optical signaling to control the circuit switching functions. To implement CSPIN, the CSPIN router is proposed which uses electro-optical tuned microring resonators. The analysis based on the synthesis result of the CSPIN router shows that significant savings in power and path setup latency are achieved by the proposed CSPIN architecture.

· Hybrid Opto-Electronic NoC Architecture (IJLT2014)
      Hybrid optoelectronic NoCs provide a more practical solution by using the electronic network for local communication while the optical network for global communication. This paper explores how to efficiently combine optical and electronic networks to build a hybrid NoC. A butterfly fat tree (BFT)-based hybrid optoelectronic NoC architecture is proposed using the generic wavelength-routed optical router (GWOR). Simulation results demonstrate that, compared with electronic Mesh- and CMesh-based NoCs, the proposed hybrid NoC achieves the best power efficiency with comparable throughput and significantly reduces the latency under localized traffic.