Multi-Board-Based Testbed in Support of Future Many-Core and System-on-Chip Research and Design Exploration
Envisioning the needs of building future large-scale many-core computing systems (with 100-1000 various types of cores such as CPU, DSP, memory, and other IP cores), in this project, we will develop a highly scalable and reconfigurable multi-board-based testbed which can emulate and validate future large-scale many-core and system-on-chip (SoC) systems. In specific, this testbed will be able to efficiently and effectively emulate all the functionalities that are perceived at both the Network-on-Chip (NoC) and the full-system levels. At the NoC level, this developed testbed shall be able to emulate every aspect of an NoC architecture along with its operational scenarios which encompasses the functions of traffic pattern generation, routing/switching, flow control, process monitoring and evaluation, result data collection and analysis. At the full-system SoC level (NoC + Cores), this instrument again is capable of emulating all the aspects of a complete many-core/SoC system with cycle or transaction level accuracy.
Figure 1 Interconnection of eight module boards with an optical interconnection network board.
The proposed testbed consists of the hardware infrastructure and software part. As shown in Fig. 1, the hardware infrastructure is built upon multiple optically interconnected emulation module board with each board housing multiple state-of-the-art FPGA chips. The hardware design libraries (NoC components and IP cores) will be developed and made as open source. The software part includes the integrated emulation environment (IEE) tools and the emulation program repository. The IEE is responsible for compiling an application program, simulating the application functions, setting up the emulation parameters, controlling and monitoring the emulation process of an NoC architecture and/or a complete SoC system, and displaying result statistics in real time. The emulation program repository to be developed provides emulation programs for SPLASH2 and PARSEC benchmarks and typical NoC applications.
By effectively exploring the massive parallelism, ease of reconfigurability of the testbed, unprecedented level of speed/performance improvement, accuracy, and flexibility can be achieved. Enabled by the novel optical interconnection network, the testbed is highly scalable and expandable to lend itself to emulate future photonic and hybrid photonic-electronic NoC-based many-core/SoC systems. This new instrument can also serve as an excellent educational tool to help graduate and undergraduate students acquire valuable research skills and hardware/software development experiences.
· Wavelength-Routed Optical Networks Built with Comb Switches (IPTL2013, IPC2013, GroupIV2012)
In this work, comb switches are used to improve the bandwidth of wavelength-routed optical NoCs without changing the network structure. A method is proposed to determine a minimal size comb MRR with given number of resonance wavelengths. We also show that comb switches can used to simplify Banyan-type wavelength-routed optical networks. A four-port wavelength-routed optical router is designed and fabricated on silicon-on-insulator wafer. The device has a small footprint (~78x100µm^2) and low power consumption (6.58 mW).